Method for fabricating semiconductor device with damascene structure by using etch stop layer

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12142518
APP PUB NO 20230307289A1
SERIAL NO

17701949

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Abstract

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The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

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Patent Owner(s)

Patent OwnerAddress
NANYA TECHNOLOGY CORPORATIONNO 98 NANLIN RD TAISHAN DIST NEW TAIPEI CITY 243

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pan, Wei-Chen New Taipei, TW 12 3

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