Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12141082
APP PUB NO 20230289304A1
SERIAL NO

17691276

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Abstract

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A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.

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Patent Owner(s)

Patent OwnerAddress
NVIDIA CORPORATION2788 SAN TOMAS EXPRESSWAY SANTA CLARA CA 95051

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choquette, Jack Santa Clara, US 47 253
Gadre, Shirish Santa Clara, US 82 831
Giroux, Oliver Santa Clara, US 2 23
Kaatz, Alan Santa Clara, US 24 10
Krashinsky, Ronny Santa Clara, US 21 59
Minkin, Alexander L Santa Clara, US 36 332
Patel, Manan Santa Clara, US 44 267
Schottmiller, Jeff Santa Clara, US 3 4
Tran, John Santa Clara, US 37 314

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