Semiconductor memory devices and methods of operating semiconductor memory devices
Number of patents in Portfolio can not be more than 2000
United States of America
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Nov 5, 2024
Grant Date -
Jul 13, 2023
app pub date -
Feb 24, 2023
filing date -
Feb 24, 2023
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Abstract
A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
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