Semiconductor memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Nov 5, 2024
Grant Date -
Sep 28, 2023
app pub date -
Aug 26, 2022
filing date -
Aug 26, 2022
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.
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