Adaptive lower power state entry and exit
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United States of America
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Nov 5, 2024
Grant Date -
Oct 1, 2020
app pub date -
May 28, 2020
filing date -
May 28, 2020
priority date (Note) -
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Abstract
Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.
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