SM3 hash algorithm acceleration processors, methods, systems, and instructions
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
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Oct 29, 2024
Grant Date -
Jan 6, 2022
app pub date -
Sep 20, 2021
filing date -
Sep 20, 2021
priority date (Note) -
In Force
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Importance

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Abstract
A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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INTEL CORPORATION | SANTA CLARA CA |
International Classification(s)

- 2021 Application Filing Year
- H04L Class
- 33798 Applications Filed
- 20288 Patents Issued To-Date
- 60.03 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Gueron, Shay | Haifa, IL | 147 | 2415 |
# of filed Patents : 147 Total Citations : 2415 | |||
Krasnov, Vlad | Nesher, IL | 32 | 601 |
# of filed Patents : 32 Total Citations : 601 |
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- 0 Citation Count
- H04L Class
- 0 % this patent is cited more than
- 1 Age
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