Systems and methods for PLL gain calibration
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United States of America
Stats
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Oct 29, 2024
Grant Date -
Sep 19, 2024
app pub date -
Mar 14, 2023
filing date -
Mar 14, 2023
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.
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International Classification(s)
- 2023 Application Filing Year
- H03L Class
- 302 Applications Filed
- 126 Patents Issued To-Date
- 41.73 % Issued To-Date
Cited Art Landscape
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- 0 Citation Count
- H03L Class
- 0 % this patent is cited more than
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