Methods and apparatus to balance propagation delay and bus emissions in transceivers

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12132481
APP PUB NO 20230188138A1
SERIAL NO

17709734

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Abstract

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Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENT INCORPORATED12500 TI BOULEVARD M/S 3999 DALLAS TX 75243

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhattacharya, Upasana Bengaluru, IN 2 0
Gupta, Lokesh Kumar Bangalore, IN 16 32

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