Three-dimensional memory device containing self-aligned isolation strips and methods for forming the same
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United States of America Patent
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Oct 22, 2024
Grant Date -
Jul 20, 2023
app pub date -
Jan 18, 2022
filing date -
Jan 18, 2022
priority date (Note) -
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Abstract
A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
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