Adjustable phase locked loop
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United States of America Patent
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Oct 22, 2024
Grant Date -
Nov 30, 2023
app pub date -
Aug 11, 2023
filing date -
Sep 21, 2021
priority date (Note) -
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Abstract
In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.
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