Asymmetric semiconductor device including LDD region and manufacturing method thereof
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United States of America Patent
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Oct 22, 2024
Grant Date -
Dec 22, 2022
app pub date -
Jan 26, 2022
filing date -
Jun 21, 2021
priority date (Note) -
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Abstract
A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.
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