Anti-fuse memory reading circuit with controllable reading time
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United States of America Patent
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Oct 15, 2024
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N/A
app pub date -
Sep 29, 2022
filing date -
Dec 3, 2021
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Abstract
In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.
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