Memory controller performing data training, system-on-chip including the memory controller, and operating method of the memory controller
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United States of America Patent
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Oct 15, 2024
Grant Date -
Feb 8, 2024
app pub date -
Oct 19, 2023
filing date -
Jun 8, 2021
priority date (Note) -
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Abstract
A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
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