Signal synchronization adjustment method and signal synchronization adjustment circuit

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United States of America Patent

PATENT NO 12119041
APP PUB NO 20240233807A1
SERIAL NO

18093817

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Abstract

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The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

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Patent Owner(s)

Patent OwnerAddress
INTEGRATED SILICON SOLUTION INC1623 BUCKEYE DR MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bae, Seung Cheol Milpitas, US 6 19
Jun, Sang Min Milpitas, US 9 4
Lee, Kang Min Milpitas, US 26 178
Lee, Kwang Kyung Milpitas, US 4 0
Yoon, Sun Byeong Milpitas, US 6 0
Yoon, Young Jin Milpitas, US 21 79

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