Refresh circuit, memory, and refresh method
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United States of America Patent
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Oct 15, 2024
Grant Date -
Sep 7, 2023
app pub date -
Sep 30, 2022
filing date -
Mar 4, 2022
priority date (Note) -
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Abstract
A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.
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