Memory device for wafer-on-wafer formed memory and logic
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 8, 2024
Grant Date -
Feb 16, 2023
app pub date -
Apr 4, 2022
filing date -
Apr 4, 2022
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully