Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module
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United States of America Patent
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Oct 8, 2024
Grant Date -
Dec 7, 2023
app pub date -
Aug 24, 2023
filing date -
Sep 10, 2021
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Abstract
A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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