Pillar-shaped semiconductor device and manufacturing method thereof
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United States of America
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Sep 17, 2024
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N/A
app pub date -
Oct 4, 2021
filing date -
Oct 4, 2021
priority date (Note) -
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Abstract
In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.
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