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Abstract

A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

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First Claim