Memory devices having vertical transistors in staggered layouts
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United States of America Patent
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Sep 3, 2024
Grant Date -
May 4, 2023
app pub date -
Dec 1, 2021
filing date -
Oct 31, 2021
priority date (Note) -
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Abstract
In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.
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