Nanofabrication and design techniques for 3D ICs and configurable ASICs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 12079557
APP PUB NO 20210350061A1
SERIAL NO

17273713

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

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Patent Owner(s)

Patent OwnerAddress
BOARD OF REGENTS THE UNIVERSITY OF TEXAS SYSTEM210 WEST 7TH ST AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ajay, Paras Austin, US 27 36
Kulkarni, Jaydeep Austin, US 23 52
McDermott, Mark Austin, US 12 13
Sayal, Aseem Austin, US 12 10
Sreenivasan, Sidlgata V Austin, US 214 5594

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