Resumable instruction generation
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United States of America Patent
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Aug 27, 2024
Grant Date -
Mar 30, 2023
app pub date -
Dec 2, 2022
filing date -
Dec 2, 2022
priority date (Note) -
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status (Latency Note)
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Abstract
A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.
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