Cache structure and utilization

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12066975
SERIAL NO

17429291

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Abstract

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Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anantaraman, Aravindh Folsom, US 67 457
Andrei, Valentin San Jose, US 55 444
Appu, Abhishek R El Dorado Hills, US 561 2990
Coleman, Sean Folsom, US 14 91
George, Varghese Folsom, US 193 2021
Jayakrishna, P S Bangalore KA, IN 1 23
Koker, Altug El Dorado Hills, US 565 3602
MacPherson, Mike Portland, US 57 561
Maiyuran, Subramaniam Gold River, US 287 2591
Ould-Ahmed-Vall, ElMoustapha Chandler, US 606 5412
Pattabhiraman, K Bangalore KA, IN 3 48
Ranganathan, Vasanth El Dorado Hills, US 204 1602
Ray, Joydeep Folsom, US 614 3794
Striramassarma, Lakshminarayanan Folsom, US 64 598
Surti, Prasoonkumar Folsom, US 421 2553

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