Logic circuit, processing unit, electronic component, and electronic device
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United States of America Patent
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Aug 6, 2024
Grant Date -
Oct 13, 2022
app pub date -
Jun 21, 2022
filing date -
Oct 10, 2014
priority date (Note) -
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Abstract
A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
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