Semiconductor device having contact plug connected to gate structure on PMOS region
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United States of America Patent
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Aug 6, 2024
Grant Date -
Nov 16, 2023
app pub date -
Jul 27, 2023
filing date -
Jul 27, 2023
priority date (Note) -
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Abstract
A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.
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