Circuits and methods for set and reset signals
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United States of America Patent
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Jul 23, 2024
Grant Date -
May 4, 2023
app pub date -
Nov 4, 2021
filing date -
Nov 4, 2021
priority date (Note) -
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Abstract
In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.
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