Scan chain designing and circuit testing method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 12044721
APP PUB NO 20230213575A1
SERIAL NO

18049521

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Abstract

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A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.

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Patent Owner(s)

Patent OwnerAddress
REALTEK SEMICONDUCTOR CORPORATIONNO 2 INNOVATION ROAD II HSINCHU SCIENCE PARK HSINCHU 300

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Ying-Yen Hsinchu, TW 28 30
Wang, Shiou Wen Hsinchu, TW 1 0
Yang, Yu Yen Hsinchu, TW 1 0

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