Systems and techniques for timing mismatch reduction

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United States of America Patent

PATENT NO 12021531
APP PUB NO 20240072774A1
SERIAL NO

17895826

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Abstract

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Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 SOUTH FEDERAL WAY BOISE ID 83716-9632

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Morishita, Yoshihito Shibuya-ku, JP 35 340

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