Overlay mark forming Moire pattern, overlay measurement method using same, and manufacturing method of semiconductor device using same
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United States of America Patent
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Jun 25, 2024
Grant Date -
Sep 7, 2023
app pub date -
May 9, 2023
filing date -
Jan 20, 2022
priority date (Note) -
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Abstract
An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.
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