Digital system synchronization
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United States of America
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Jun 25, 2024
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app pub date -
Dec 15, 2021
filing date -
Dec 15, 2021
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Abstract
A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal.
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