Stacked semiconductor die architecture with multiple layers of disaggregation
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United States of America Patent
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Jun 18, 2024
Grant Date -
Apr 6, 2023
app pub date -
Dec 13, 2022
filing date -
Jan 3, 2018
priority date (Note) -
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Abstract
Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.
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