Method and system for low noise sub-sampling phase lock loop (PLL) architecture with automatic dynamic frequency acquisition
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United States of America Patent
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May 28, 2024
Grant Date -
Jan 4, 2024
app pub date -
Aug 25, 2022
filing date -
Jun 29, 2022
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Abstract
A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.
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