Bias circuit and power amplifier circuit
Number of patents in Portfolio can not be more than 2000
United States of America
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May 21, 2024
Grant Date -
N/A
app pub date -
Aug 29, 2019
filing date -
Aug 29, 2019
priority date (Note) -
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Abstract
A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.
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