Quadrature circuit interconnect architecture with clock forwarding
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United States of America Patent
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May 7, 2024
Grant Date -
Mar 21, 2024
app pub date -
Sep 20, 2022
filing date -
Sep 20, 2022
priority date (Note) -
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Abstract
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
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