Method for manufacturing semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11977099
APP PUB NO 20210048450A1
SERIAL NO

16967246

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Abstract

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A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.

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Patent Owner(s)

Patent OwnerAddress
HITACHI HIGH-TECH CORPORATION17-1 TORANOMON 1-CHOME MINATO-KU TOKYO 105-6409

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujimura, Toru Tokyo, JP 20 95
Hirano, Ryo Tokyo, JP 51 188
Kageyama, Akira Tokyo, JP 41 355
Kato, Shigehiko Tokyo, JP 4 2
Komori, Masaaki Tokyo, JP 19 166
Mizuno, Takayuki Tokyo, JP 84 596
Nara, Yasuhiko Tokyo, JP 51 566
Ohki, Katsuo Tokyo, JP 6 74
Ohtaki, Tomohisa Tokyo, JP 23 174

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