Sub-cell, mac array and bit-width reconfigurable mixed-signal in-memory computing module

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United States of America Patent

PATENT NO 11948659
APP PUB NO 20220351761A1
SERIAL NO

17762447

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Abstract

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A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.

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Patent Owner(s)

Patent OwnerAddress
REEXEN TECHNOLOGY CO LTD310 BUILDING 1 SHENZHEN NEW GENERATION INDUSTRIAL PARK NO 136 ZHONGKANG ROAD MEIDU COMMUNITY MEILIN STREET FUTIAN DISTRICT SHENZHEN GUANGDONG 518049

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Hongjie Guangdong, CN 34 147
Morgado, Alonso Villach, AT 5 25
Webb, Neil Kilchberg, CH 4 10
Yang, Minhao Zürich, CH 5 9

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