Level converter and circuit arrangement comprising such level converters
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United States of America Patent
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Mar 26, 2024
Grant Date -
Mar 2, 2023
app pub date -
Apr 27, 2021
filing date -
Apr 29, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.
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