Dual chip clock synchronization
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United States of America
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Mar 26, 2024
Grant Date -
N/A
app pub date -
Mar 31, 2022
filing date -
Mar 31, 2022
priority date (Note) -
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Abstract
Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.
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