Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
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United States of America Patent
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Mar 12, 2024
Grant Date -
Nov 17, 2022
app pub date -
May 17, 2021
filing date -
May 17, 2021
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Abstract
An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.
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