Sparsity-aware reconfigurable compute-in-memory (CIM) static random access memory (SRAM)
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United States of America Patent
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Mar 12, 2024
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Jun 8, 2023
app pub date -
Dec 8, 2021
filing date -
Dec 8, 2021
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Abstract
Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.
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