Decoupling atomicity from operation size
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United States of America
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Feb 27, 2024
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app pub date -
Jun 22, 2020
filing date -
Jun 22, 2020
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Abstract
In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.
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