Duty-cycle corrector circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 16, 2024
Grant Date -
Jul 27, 2023
app pub date -
Dec 23, 2022
filing date -
May 6, 2021
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2022 Application Filing Year
- H03L Class
- 440 Applications Filed
- 300 Patents Issued To-Date
- 68.19 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 1 Citation Count
- H03L Class
- 92.74 % this patent is cited more than
- 1 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Jul 16, 2027 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 16, 2031 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 16, 2035 |
