Integrated counter in memory device
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United States of America Patent
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Jan 2, 2024
Grant Date -
Jan 19, 2023
app pub date -
Dec 3, 2020
filing date -
Dec 12, 2019
priority date (Note) -
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Abstract
A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.
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