Low-k gate spacer and methods for forming the same
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United States of America Patent
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Dec 26, 2023
Grant Date -
Feb 25, 2021
app pub date -
Nov 5, 2020
filing date -
Nov 14, 2017
priority date (Note) -
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Abstract
Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
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