FPGA implementation interleaved with FPGA overlay architectures for emulation
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United States of America Patent
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Dec 26, 2023
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N/A
app pub date -
Sep 23, 2019
filing date -
Sep 23, 2019
priority date (Note) -
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Abstract
A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.
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