Systems and methods for context-dependent multicore interrupt facilitation

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United States of America Patent

PATENT NO 11846973
SERIAL NO

17982916

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Abstract

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A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

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Patent Owner(s)

Patent OwnerAddress
CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD7B NIGHTINGALE WAY QUARTERMILE EDINBURGH EH3 9EG

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Deo, Sachin Austin, US 10 22
Djadi, Younes Austin, US 19 227
Hemkumar, Nariankadu D Austin, US 19 338
Li, Junsong Austin, US 31 422
Shum, Wai-Shun Austin, US 15 51
Weller, Franz Austin, US 6 46

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