Non-volatile memory (NVM) cell structure to increase reliability

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United States of America Patent

PATENT NO 11844213
APP PUB NO 20220336482A1
SERIAL NO

17854068

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Abstract

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Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Shih-Hsien Zhubei, TW 43 157
Ko, Chun-Yao Hsinchu, TW 40 149
Tsui, Felix Ying-Kit Cupertino, US 70 246

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