Memory system with cached memory module operations

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United States of America Patent

PATENT NO 11836099
SERIAL NO

17548510

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Abstract

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Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hampel, Craig Los Altos, US 35 998
Linstadt, John Eric Palo Alto, US 166 392
Ware, Frederick A Los Altos Hills, US 803 11661
Wright, Kenneth L Sunnyvale, US 104 874

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