System of free running oscillators for digital system clocking immune to process, voltage and temperature (PVT) variations
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United States of America Patent
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Nov 28, 2023
Grant Date -
Mar 23, 2023
app pub date -
Jul 29, 2022
filing date -
Mar 28, 2017
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Abstract
A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.
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