Word line drive circuit and dynamic random access memory
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United States of America Patent
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Nov 28, 2023
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N/A
app pub date -
Aug 26, 2021
filing date -
Oct 23, 2020
priority date (Note) -
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Abstract
The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.
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